CECS 301 - Computer Logic Design II

California State University Long Beach (F20, S21, F21, S22, F22, S23, F23)

Course Objectives:

CLO1: Identifying, analyzing, and designing combinational circuits
CLO2: Identifying, analyzing, and designing sequential circuits
CLO3: Describing, explaining, and using timing analysis of combinational and sequential circuits
CLO4: Describing, comparing, and implementing different interconnection networks and routing algorithms
CLO5: Describing, comparing, and implementing different memory circuits and systems
CLO6: Identifying, explaining, and comparing different digital circuit design methods
CLO7: Writing hardware description language codes and implementing & testing logic circuits on FPGA’s.

Course Outline:

Topic 0: Course Information (Overview, Outline, Materials, Grading, Policies, Student Support, and Contact Options)
Topic 1: Combinational Circuits (Logic Gates, Boolean Algebra, Designing Combinational Circuits, Combinational Logic Minimization, Combinational Logic Blocks, Adders, and Subtractors)
Topic 2: Sequential Circuits (Basic Memory Devices, Finite State Machine, Moore & Mealy Machines, Sequence Detector, and Seven Segment)
Topic 3: Digital Timing Analysis (Contamination Delay, Propagation Delay, Glitches, Timing Graph, Arrival Times, Critical Path, False Path, Path Sensitization, Setup Time, Hold Time, and Clock Skew)
Topic 4: System Bus (Master-Slave System Bus, Bus Protocols, Interconnection Networks, Topologies, and Routing Algorithms)
Topic 5: Memory Circuits & Systems (Static Random Access Memory, Dynamic Random Access Memory, Electrically Erasable Programmable Read Only Memory, and Flash Memory)
Topic 6: Programmable Logic Devices (Basic Logic Array, Programmable Logic Array, Programmable Array Logic, Complex Programmable Logic Devices, Field Programmable Gate Arrays, and Application Specific Integrated Circuits)

CECS 361 - Digital Design Techniques and Verification

California State University Long Beach (F20, S21, F21, S22, F22, S23, F23)

Course Objectives:

CLO1: Identifying, analyzing, and designing combinational and sequential circuits
CLO2: Identifying types of verification, solving Boolean Satisfiability problem, and using binary decision diagrams
CLO3: Describing and discussing different formal design verification methods
CLO4: Describing and discussing different functional design verification methods
CLO5: Explaining and analyzing fault and defect modeling in digital circuits
CLO6: Discussing an advanced topic in computer logic design
CLO7: Writing hardware description language codes and implementing & testing logic circuits on FPGA’s.

Course Outline:

Topic 0: Course Information (Overview, Outline, Materials, Grading, Policies, Student Support, and Contact Options)
Topic 1: Combinational & Sequential Circuits (Adders, Subtractors, Shifters, Multipliers, Combinational & Sequential Circuit Design, and Cyclic Combinational Circuits)
Topic 2: Introduction to Design Verification (Types of Verification, Boolean Satisfiability Problem, Resolvent Algorithm, Binary Decision Tree, Binary Decision Diagram, and Solving SAT with BDDs)
Topic 3: Formal Design Verification (Formal Verification Characteristics, BDD-based Equivalence Checking, SAT-based Equivalence Checking, Property Specification, Property Checking, State Explosion Problem, and Automated Theorem Proving)
Topic 4: Functional Design Verification (Functional Coverage Model, Coding for Verification, Syntactical Checks, Timing Correctness, Synthesizability, Simulation-based Verification, Code Generation, Scheduling Semantics, and Emulation-based Verification)
Topic 5: Fault & Defect Modeling (Fault Abstraction Levels, Stuck-at Faults, Bridging Faults, Indistinguishable Faults, Fault Collapsing, Fault Tolerance, and Fault Simulation)
Topic 6: Logic Encryption (Traditional Logic Encryption, SAT-based Attack, Post SAT Encryption)

Northwestern University, (W16 (TA), W18 (Co-Instructor), S19 (Co-Instructor))