2024

[45] [DCAS '24] J. Maynard and A. Rezaei, “Reconfigurable Run-Time Hardware Trojan Mitigation for Logic-Locked Circuits,” In Proceedings of 17th IEEE Dallas Circuits and Systems Conference (DCAS), pp. 1-6, 2024, USA. (DOI: 10.1109/DCAS61159.2024.10539881)  [PDF] [Repo]

[44] [DATE '24] M. Dominguez and A. Rezaei, “CycPUF: Cyclic Physical Unclonable Function,” In Proceedings of 27th Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6, 2024, Spain. (25% acceptance rate) (To Appear) [PDF] [Repo]

[43] [DATE '24] R. Vishwakarma and A. Rezaei, “Uncertainty-Aware Hardware Trojan Detection Using Multimodal Deep Learning,” In Proceedings of 27th Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6, 2024, Spain. (25% acceptance rate) (To Appear) [PDF] [Repo]

[42] [HaSS '24] Y. Aghamohammadi and A. Rezaei, “Machine Learning-based Security Evaluation and Overhead Analysis of Logic Locking,” In Journal of Hardware and Systems Security (HaSS-Springer), 2024. (ISSN: 2509-3436) (DOI: 10.1007/s41635-024-00144-8) [PDF] [Repo]

[41] [ASP-DAC '24] Y. Aghamohammadi and A. Rezaei, “LIPSTICK: Corruptibility-Aware and Explainable Graph Neural Network-based Oracle-Less Attack on Logic Locking,” In Proceedings of 29th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 606-611, 2024, South Korea. (DOI: 10.1109/ASP-DAC58780.2024.10473982) (29% acceptance rate) [PDF] 

2023 

[40] [ICCAD '23] R. Vishwakarma and A. Rezaei, “Risk-Aware and Explainable Framework for Ensuring Guaranteed Coverage in Evolving Hardware Trojan Detection,” In Proceedings of 42nd International Conference on Computer Aided Design (ICCAD), pp. 1-9, 2023, USA. (DOI: 10.1109/ICCAD57390.2023.10323655) (23% acceptance rate) [PDF] [Repo]

[39] [Access '23] J. Hwang, G. Kale, P. Patel, R. Vishwakarma, M. Aliasgari, A. Hedayatipour, A. Rezaei, and H. Sayadi, “Machine Learning in Chaos-based Encryption: Theory, Implementations, and Applications,” In IEEE Access, Vol. 11, pp. 125749-125767, 2023. (DOI: 10.1109/ACCESS.2023.3331320) (ISSN: 2169-3536) (Impact Factor: 3.9) [PDF] 

[38] [GLSVLSI '23] Y. Aghamohammadi and A. Rezaei, “CoLA: Convolutional Neural Network Model for Secure Low Overhead Logic Locking Assignment,” In Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. 339–344, 2023, USA. (DOI: 10.1145/3583781.3590219) [PDF] [Repo]

[37] [Discover IoT '23] R. Vishwakarma, R. Monani, A. Hedayatipour, and A. Rezaei, “Reliable and Secure Memristor-based Chaotic Communication Against Eavesdroppers and Untrusted Foundries,” In Discover Internet of Things (Discover IoT-Springer), Vol. 3, Article 2, 2023. (DOI: 10.1007/s43926-023-00029-2) (ISSN: 2730-7239) [PDF] [Repo]

[36] [ISQED '23] J. Maynard and A. Rezaei, “DK Lock: Dual Key Logic Locking Against Oracle-Guided Attacks,” In Proceedings of 24th International Symposium on Quality Electronic Design (ISQED), pp. 1-7, 2023, USA. (DOI: 10.1109/ISQED57927.2023.10129368) [PDF] [Repo]

[35] [ISQED '23] R. Vishwakarma, R. Monani, A. Rezaei, H. Sayadi, M. Aliasgari, and A. Hedayatipour, “Attacks on Continuous Chaos Communication and Remedies for Resource Limited Devices,” In Proceedings of 24th International Symposium on Quality Electronic Design (ISQED), pp. 1-8, 2023, USA. (DOI: 10.1109/ISQED57927.2023.10129355) [PDF] [Repo]

2022

[34] [ICCAD '22] A. Rezaei, R. Afsharmazayejani, and J. Maynard, “Evaluating the Security of eFPGA-based Redaction Algorithms,” In Proceedings of 41st International Conference on Computer Aided Design (ICCAD), Article 154, pp. 1-7, 2022, USA. (DOI: 10.1145/3508352.3549425) (22% acceptance rate) [PDF]

[33] [IGESSC '22] R. Monani, B. Rogers, A. Rezaei, and A. Hedayatipour, “Implementation of Chaotic Encryption Architecture on FPGA for On-Chip Secure Communication,” In Proceedings of IEEE Green Energy and Smart Systems Conference (IGESSC), pp. 1-6, 2022, USA. (DOI:10.1109/IGESSC55810.2022.9955334) [PDF]

[32] [HOST '22] A. Rezaei, A. Hedayatipour, H. Sayadi, M. Aliasgari, and H. Zhou, “Global Attack and Remedy on IC-Specific Logic Encryption,” In Proceedings of International Symposium on Hardware Oriented Security and Trust (HOST), pp. 145-148, 2022, USA. (DOI: 10.1109/HOST54066.2022.9840128) [PDF]

[31] [GLSVLSI '22] R. Afsharmazayejani, H. Sayadi, and A. Rezaei, “Distributed Logic Encryption: Essential Security Requirements and Low-Overhead Implementation,” In Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. 127-131, 2022, USA. (DOI: 10.1145/3526241.3530372) (26% acceptance rate) [PDF]

[30] [GLSVLSI '22] Z. He, A. Rezaei, H. Homayoun, and H. Sayadi, “Deep Neural Network and Transfer Learning for Accurate Hardware-Based Zero-Day Malware Detection,” In Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. 27-32, 2022, USA. (DOI: 10.1145/3526241.3530326) (29% acceptance rate) [PDF]

2021

[29] [SVCC '21] A. Hedayatipour, R. Monani, A. Rezaei, M. Aliasgari, and H. Sayadi, “A Comprehensive Analysis of Chaos-Based Secure Systems,” In Proceedings of Silicon Valley Cybersecurity Conference (SVCC), pp. 90-105, 2021, USA. (DOI: 10.1007/978-3-030-96057-5_7) [PDF]

[28] [IOLTS '21] Y. Gao, H. M. Makrani , M. Aliasgari, A. Rezaei, J. Lin, H. Homayoun, and H. Sayadi, “Adaptive-HMD: Accurate and Cost-Efficient Machine Learning-Driven Framework for Online Malware Detection using Microarchitectural Events,” In Proceedings of 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 1-7, 2021, Italy. (DOI: 10.1109/IOLTS52814.2021.9486701) [PDF]

[27] [ICRA '21] F. Tajdari, M. Tajdari, and A. Rezaei, “Discrete Time Delay Feedback Control of Stewart Platform with Intelligent Optimizer Weight Tuner,” In Proceedings of International Conference on Robotics and Automation (ICRA), pp. 12701-12707, 2021, China. (DOI: 10.1109/ICRA48506.2021.9561010) (48% acceptance rate) [PDF]

[26] [DATE '21] A. Rezaei and H. Zhou, “Sequential Logic Encryption Against Model Checking Attack,” In Proceedings of 24th Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1178-1181, 2021, France. (DOI: 10.23919/DATE51398.2021.9474002) (24% acceptance rate) [PDF]

2020

[25] [arXiv Archive '20] S. Kong, Y. Li, J. Wang, A. Rezaei, and H. Zhou, “KNN-enhanced Deep Learning Against Noisy Labels,” In arXiv Archive, arXiv:2012.04224, 2020. [PDF]

[24] [arXiv Archive '20] B. Tan, R. Karri, N. Limaye, A. Sengupta, O. Sinanoglu, M. M. Rahman, S. Bhunia, D. Duvalsaint, A. Rezaei, et al., “Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking,” In arXiv Archive, arXiv:2006.06806, 2020. [PDF]

[23] [DATE '20] A. Rezaei, Y. Shen, and H. Zhou, “Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation,” In Proceedings of 23rd Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 13-18, 2020, France. (DOI: 10.23919/DATE48585.2020.9116500) (26% acceptance rate) [PDF]

2019

[22] [ICCAD '19] H. Zhou, A. Rezaei, and Y. Shen, “Resolving the Trilemma in Logic Encryption,” In Proceedings of 38th International Conference on Computer Aided Design (ICCAD), pp. 1-8, 2019, USA. (DOI: 10.1109/ICCAD45719.2019.8942076) (24% acceptance rate) [PDF]

[21] [ePrint Archive '19] H. Zhou, Y. Shen, and A. Rezaei, “Vulnerability and Remedy of Stripped Function Logic Locking,” In Cryptology ePrint Archive, report 2019/139, 2019. [PDF]

[20] [ISVLSI '19] A. Rezaei, J. Gu, and H. Zhou, “Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries,” In Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 535-540, 2019, USA. (DOI: 10.1109/ISVLSI.2019.00102) (35% acceptance rate) [PDF]

[19] [DATE '19] Y. Shen, Y. Li, S. Kong, A. Rezaei, and H. Zhou, “SigAttack: New High-level SAT-based Attack on Logic Encryptions,” In Proceedings of 22nd Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 940-943, 2019, Italy. (DOI: 10.23919/DATE.2019.8714924) (24% acceptance rate) [PDF]

[18] [ASP-DAC '19] A. Rezaei, Y. Li, Y. Shen, S. Kong, and H. Zhou, “CycSAT-Unresolvable Cyclic Logic Encryption Using Unreachable States,” In Proceedings of 24th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 358-363, 2019, Japan. (DOI: 10.1145/3287624.3287691) (35% acceptance rate) [PDF]

[17] [ASP-DAC '19] Y. Shen, Y. Li, A. Rezaei, S. Kong, D. Dlott, and H. Zhou, “BeSAT: Behavioral SAT-based Attack on Cyclic Logic Encryption,” In Proceedings of 24th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 657-662, 2019, Japan. (DOI: 10.1145/3287624.3287670) (35% acceptance rate) [PDF]

[16] [WINE '19] S. H. Mortazavi, R. Akbar, F. Safaei, and A. Rezaei, “A Fault-Tolerant and Congestion-Aware Architecture for Wireless Networks-on-Chip,” In Wireless Networks (WINE-Springer), Vol. 25, Issue 6, pp. 3675-3687, 2019. (DOI: 10.1007/s11276-019-01962-3) (ISSN: 1022-0038) (Impact Factor: 3.0) [PDF]

[15] [SUPE '19] F. Yazdanpanah, R. Afsharmazayejani, M. Alaei, A. Rezaei, and M. Daneshtalab, “An Energy-Efficient Partition-based XYZ-Planar Routing Algorithm for a Wireless Network-on-Chip,” In The Journal of Supercomputing (SUPE-Springer), Vol. 75, Issue 2, pp. 837-861, 2019. (DOI: 10.1007/s11227-018-2617-x) (ISSN: 0920-8542) (Impact Factor: 3.3) [PDF]

2018

[14] [ADCOM '18] A. Rezaei, M. Daneshtalab, and H. Zhou “Multiobjectivism in Dark Silicon Age,” In Advances in Computers (ADCOM-Elsevier), Vol. 110, pp. 83-126, 2018. (DOI: 10.1016/bs.adcom.2018.03.012) (ISSN: 0065-2458) (Impact Factor: 2.7) [PDF]

[13] [ARC '18] R. Afsharmazayejani, F. Yazdanpanah, A. Rezaei, M. Alaei, and M. Daneshtalab, “HoneyWiN: Novel Honeycomb-based Wireless NoC Architecture in Many-Core Era,” In Proceedings of 14th International Symposium on Applied Reconfigurable Computing (ARC), pp. 304-316, 2018, Greece. (DOI: 10.1007/978-3-319-78890-6_25) (37% acceptance rate) [PDF]

[12] [DATE '18] A. Rezaei, Y. Shen, S. Kong, J. Gu, and H. Zhou, “Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks,” In Proceedings of 21st Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 85-90, 2018, Germany. (DOI: 10.23919/DATE.2018.8341984) (24% acceptance rate) [PDF]

[11] [DATE '18] Y. Shen, A. Rezaei, and H. Zhou, “SAT-based Bit-flipping Attack on Logic Encryptions,” In Proceedings of 21st Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 629-632, 2018, Germany. (DOI: 10.23919/DATE.2018.8342086) (24% acceptance rate) [PDF]

[10] [ASP-DAC '18] Y. Shen, A. Rezaei, and H. Zhou, “A Comparative Investigation of Approximate Attacks on Logic Encryptions,” In Proceedings of 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 271-276, 2018, Korea. (DOI: 10.1109/ASPDAC.2018.8297317) (31% acceptance rate) [PDF]

2017

[9] [PDP '17] A. Rezaei, D. Zhao, M. Daneshtalab, and H. Zhou, “Multi-Objective Task Mapping Approach for Wireless NoC in Dark Silicon Age,” In Proceedings of 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp. 589-592, 2017, Russia. (DOI: 10.1109/PDP.2017.12) (30% acceptance rate) [PDF]

[8] [MICPRO '17] A. Rezaei, M. Daneshtalab, and D. Zhao, “CAP-W: Congestion-Aware Platform for Wireless-based Network-on-Chip in Many-Core Era,” In Microprocessors and Microsystems (MICPRO-Elsevier), Vol. 52, pp. 23-33, 2017. (DOI: 10.1016/j.micpro.2017.05.014) (ISSN: 0141-9331) (Impact Factor: 2.6) [PDF]

2016

[7] [DAC '16] A. Rezaei, D. Zhao, M. Daneshtalab, and H. Wu, “Shift Sprinting: Fine-Grained Temperature-Aware NoC-based MCSoC Architecture in Dark Silicon Age,” In Proceedings of 53rd Design Automation Conference (DAC), Article 155, 2016, USA. (DOI: 10.1145/2897937.2898090) (18% acceptance rate) [PDF]

[6] [SOCC '16] A. Rezaei, M. Daneshtalab, D. Zhao, and M. Modarressi, “SAMi: Self-Aware Migration Approach for Congestion Reduction in NoC-based MCSoC,” In Proceedings of 29th International System-on-Chip Conference (SOCC), pp. 145-150, 2016, USA. (DOI: 10.1109/SOCC.2016.7905455) (35% acceptance rate) [PDF]

[5] [SOCC '16] S. Maabi, F. Safaei, A. Rezaei, M. Daneshtalab, and D. Zhao, “ERFAN: Efficient Reconfigurable Fault-Tolerant Deflection Routing Algorithm for 3-D Network-on-Chip,” In Proceedings of 29th International System-on-Chip Conference (SOCC), pp. 306-311, 2016, USA. (DOI: 10.1109/SOCC.2016.7905497) (35% acceptance rate) [PDF]

[4] [PDP '16] A. Rezaei, M. Daneshtalab, M. Palesi, and D. Zhao, “Efficient Congestion-Aware Scheme for Wireless On-Chip Networks,” In Proceedings of 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp. 742-749, 2016, Greece. (DOI: 10.1109/PDP.2016.88) (30% acceptance rate) [PDF]

[3] [COMPELEC '16] A. Rezaei, M. Daneshtalab, F. Safaei, and D. Zhao, “Hierarchical Approach for Hybrid Wireless Network-on-Chip in Many-core Era,” In Computers & Electrical Engineering (COMPELEC-Elsevier), Vol. 51, pp. 225–234, 2016. (DOI: 10.1016/j.compeleceng.2015.10.007) (ISSN: 0045-7906) (Impact Factor: 4.3) [PDF]

2015

[2] [PDP '15] A. Rezaei, M. Daneshtalab, D. Zhao, F. Safaei, X. Wang, and M. Ebrahimi, “Dynamic Application Mapping Algorithm for Wireless Network-on-Chip,” In Proceedings of 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp. 421-424, 2015, Finland. (DOI: 10.1109/PDP.2015.14) (28% acceptance rate) [PDF]

2014

[1] [HPCS '14] A. Rezaei, F. Safaei, M. Daneshtalab, and H. Tenhunen, “HiWA: A Hierarchical Wireless Network-on-Chip Architecture,” In Proceedings of 12th International Conference on High Performance Computing & Simulation (HPCS), pp. 499-505, 2014, Italy. (DOI: 10.1109/HPCSim.2014.6903726) (38% acceptance rate) [PDF]